ISO 26262 Academy · Learning path · open to read
Hardware Safety Engineer
Part 5 end to end: mechanisms, metrics, FMEDA and qualification of safety-related hardware.
- 4 weeks
- 22 items
- 13.6 hours
- 1 free with an account
Career Path gives you an assessment and a roadmap based on your experience and goals. This track is the fixed schedule for one role.
The schedule
Week by week.
Guides, practice and checks in the order they build on each other. Open a guide to see what it covers; each item shows every plan that includes it.
- Week 1Functional safety foundations → Hardware development essentials3h 28m
- QuizCalibration: foundations12 questions20mPro plan pricingExpert plan pricing
- ReadHardware development per Part 515mExpert plan pricing
- ReadSafety mechanisms & diagnostics1h 10mExpert plan pricing
- ReadProcess: Hardware Design and Safety Analysis25mPro plan pricingExpert plan pricing
- QuizQuiz: hardware essentials10 questions18mPro plan pricingExpert plan pricing
- ReadHardware metrics (part 1 of 2)First half: failure rates, SPFM and LFM.1hPro plan pricingExpert plan pricing
- Week 2Hardware architectural metrics → FMEDA & dependent failures3h 52m
- ReadHardware metrics (part 2 of 2)Second half: PMHF and evaluation against targets.55mPro plan pricingExpert plan pricing
- SimulatorSimulator: Markov analysis45mFree plan pricingPro plan pricingExpert plan pricing
- QuizQuiz: hardware metrics12 questions22mPro plan pricingExpert plan pricing
- ReadFMEDA50mExpert plan pricing
- SimulatorSimulator: run an FMEDA1hExpert plan pricing
- Week 3FMEDA & dependent failures → Qualification & interfaces3h 48m
- ReadDependent failure analysis45mExpert plan pricing
- SimulatorSimulator: run a DFA45mPro plan pricingExpert plan pricing
- QuizQuiz: FMEDA & DFA10 questions18mPro plan pricingExpert plan pricing
- ReadHardware element evaluation30mExpert plan pricing
- ReadProcess: Hardware Integration and Verification25mPro plan pricingExpert plan pricing
- ReadHardware-software interface45mExpert plan pricing
- ReadFreedom from interference20mExpert plan pricing
- Week 4Qualification & interfaces → Semiconductors (Part 11)2h 26m
- QuizQuiz: qualification & interfaces10 questions18mPro plan pricingExpert plan pricing
- ReadSemiconductors (part 1 of 2)First half: IP, base failure rates, fault models.55mExpert plan pricing
- ReadSemiconductors (part 2 of 2)Second half: dependent failures and DFA on silicon.55mExpert plan pricing
- QuizQuiz: semiconductor safety10 questions18mPro plan pricingExpert plan pricing
Templates
119 work-product templates come with this path
Ready-to-adapt documents matched to the modules above. Reference material, not extra hours on your schedule.
Further reading
Also on this track.
Related guides outside the core schedule, for when you want to go wider.
- Vehicle domainsBattery & HV Powertrain SafetyFunctional safety for electric vehicles from cell to wheel: how lithium-ion cells fail, the BMS measurement chain, contactors and HVIL, isolation monitoring, safe torque, charging and thermal runaway, plus the FMEDA and FTTI work behind it.
- System levelEMC & Transient SafetyThe environment as a fault source: how EMI, ESD, load dump and coupled transients become random faults, the ISO 7637 / ISO 11452 / ISO 10605 standards map, immunity as a safety argument, and filtering, shielding and plausibility as safety measures.
- HardwareFPGA SafetyHardware whose circuit is data: configuration upsets and essential bits, scrubbing against the FTTI, TMR in the fabric, HDL discipline, tool confidence, and the FPGA FMEDA that closes the safety case.
- Vehicle domainsInverter and Motor Control SafetyHow a traction inverter earns its ASIL: unintended-torque hazards, Active Short Circuit vs freewheeling safe states, three-level torque monitoring, and the protection layers from gate driver to control software.
- System levelPower & Clock SupervisionThe two assumptions every other safety mechanism silently depends on: valid supply rails and a trustworthy time base. Power trees, safety PMICs, voltage monitors, sequencing, reset escalation, watchdogs, clock monitors, the independence argument, timing and energy budgets, latent-fault self-test, and the FMEDA rows they all feed.
- HardwareSoft Errors & Transient FaultsA cosmic ray hits a memory cell and your ASIL D function computes with a wrong value. This concept walks from the physics of radiation-induced bit flips through single event effects, ECC and hardened design, all the way to Part 11 quantification.
Start this path
Week one starts with a free account.
The free plan opens the first items on every track: one full concept guide, 3 templates, 1 process, the Markov and RBD simulators and 5 practice exams a month. Pro and Expert unlock the rest of the schedule.