ISO 26262 and Semiconductors
12 chapters A practical handbook for applying ISO 26262 Part 11 across digital, analog, programmable logic, multi-core SoC and sensor silicon. The standard, the annexes and the assessor-ready evidence trail, with worked FMEDA, DC, DFA and fault-injection examples.
How You Learn
Video and text stay in sync. As you scroll through the chapter, the video jumps to the matching explanation automatically.
Learning Objectives
Apply Part 11 by IC Family
Identify whether your element is digital, analog, PLD, multi-core SoC or sensor and select the correct Clause 5.x and supporting annex with justification.
Build a Defensible FMEDA at Silicon Level
Decompose die plus package FIT, classify safe faults from the exposure window, and refine block-level allocation beyond pure area proportionality.
Quantify DC for Real Safety Mechanisms
Split DC for permanent and transient faults across memory ECC, lockstep, BIST, window comparators and scrubbing, and back the number with fault-injection evidence.
Run DFA on Shared Silicon Resources
Identify Annex B coupling paths (clock, power, reset, substrate, thermal) and verify that any independence claim is supported by a documented DFA report.
Chapters
Why Silicon Is Different
Why constant-FIT models and Parts 1-10 assumptions break at advanced nodes.
Part 11 Map: Clauses & Annexes
Navigate Clause 4, the five technology-specific clauses, and the six informative annexes.
Failure Physics in Silicon
Permanent, transient, destructive and wear-out faults with JESD89C soft-error framework.
Hardware Element Catalog
Digital, analog, PLD, multi-core SoC and sensor families with per-family fault landscapes.
Distributed Development & IC as SEooC
IP vendor, foundry, OSAT and integrator collaborating through testable Assumptions of Use.
Quantifying FIT in Silicon
Handbook selection, die plus package decomposition and safe-fault exposure-window classification.
On-Chip Safety Mechanisms & DC
Diagnostic Coverage split for permanent and transient faults across memory, digital and analog SMs.
DFA at Silicon Level
Shared clock, power, reset and substrate make CCF the default; Annex B starter-list DFIs.
Multi-core & SoC Patterns
Homogeneous lockstep, heterogeneous safety island, and asymmetric monitoring patterns.
Fault Injection & EDA Qualification
Six mandatory campaign fields and EDA tool qualification per Part 8 §11.
Analog, PLD and Sensors
Annex D analog window comparators, Annex E PLD bitstream scrubbing, sensor plausibility checks.
Work Products & Pitfalls
Eight work products, ten safety-manual sections, and twelve recurring audit findings.
Interactive Diagrams & Worked Examples
Part 11 Clause Map
Navigate Clause 4 (general) and Clauses 5.1-5.5 (digital, analog, PLD, multi-core, sensors) plus the six informative annexes with cross-references to Parts 4-10.
On-Chip Safety Mechanism Cards
Per-mechanism cards for parity, SECDED, MBU strategies, scrubbing, LBIST, lockstep, window comparator and ABIST, each showing permanent and transient DC bars and the failures missed.
Multi-core Lockstep Pattern Comparison
Pure, delayed and asymmetric lockstep variants with mini block diagrams, DC formulas under the independence assumption, and the shared-resource DFIs that defeat it.
Fault-Injection Campaign Planner
Six mandatory planning fields (fault model, abstraction, fault list, workload, observation points, method) with worked example: 42k faults, post-synthesis gates, AEB workload, DC = 94.2%.
Analog Window Comparator & PLD Scrubbing
Annex D LDO with window comparator (99% perm DC, 60% aging via ABIST) plus Annex E SRAM-FPGA bitstream residual SEU after 100 ms scrubbing over an 8000 h mission.
Die + Package FMEDA Worked Example
FeaturedAnnex C numerical breakdown of a CMOS digital MCU: 0.26 FIT die (CPU, SRAM, peripherals) plus 12.41 FIT package, summed to ~13 FIT total IC with soft-error from JESD89 added separately.
Explore SimulatorsAnnex C, D and E Worked Through End to End
Each chapter is anchored in a Part 11 annex example so the math stays reproducible.
- Annex C digital FMEDA: die + package decomposition
- Annex D analog: window comparator and ABIST
- Annex E PLD: SRAM-FPGA bitstream scrubbing
- Fault-injection campaign with DC and confidence interval
- Safety manual AoU template ready for the DIA
Annex C Die + Package FMEDA
Ready to Apply ISO 26262 Part 11 to Real Silicon?
Walk through 12 chapters covering digital, analog, PLD, multi-core SoC and sensor silicon with Annex C/D/E worked examples and an assessor-ready safety case.
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