Soft Errors & Transient Faults
A single cosmic-ray neutron or a package alpha particle can flip a bit in your ASIL D microcontroller and leave the silicon undamaged. This concept takes you from the physics of radiation-induced bit flips through the full single event effect zoo, ECC and hardened design, to a reproducible ISO 26262 Part 11 transient FMEDA.
- Chapters
- 12
- Chapters
- Single-Event Effects
- 10
- Single-Event Effects
- Hardening Layers
- 6
- Hardening Layers
- Worked Transient FMEDA
- 1
- Worked Transient FMEDA
- 01When a Bit Flips
- 02Where the Particles Come From
- 03The Single Event Zoo
- 04Silicon Sensitivity & Measuring SER
- 05From Raw SER to Effective Failure Rate
Why it pays for itself
A reproducible transient FMEDA
Follow every multiplication of the three-factor pipeline - raw FIT, non-safe fraction, escape probability - through a complete worked FMEDA, so your own transient analysis has a template an assessor can audit.
Size ECC and scrubbing correctly
Choose SEC-DED versus stronger codes, set interleaving so multi-bit upsets become correctable single-bit errors, and pick scrub intervals that actually deliver the diagnostic coverage your FMEDA claims.
Derating without cheating
Apply masking and safe-fraction arguments while keeping base failure rates raw and every derating factor disclosed - the discipline that separates a defensible SER claim from an assessor finding.
What you’ll be able to do
Tell transient from permanent faults
Explain why a soft error clears on power cycle while a stuck bit does not, and book each on the right FMEDA side.
Name and place every single event effect
Distinguish SET, SEU, MCU, MBU and SEFI from destructive SEL, SEB, SEGR and SHE and classify them per Part 11.
Size ECC, interleaving and scrubbing
Choose SEC-DED versus stronger codes and set interleaving and scrub intervals to hit a transient coverage target.
Derate raw SER without cheating
Apply masking and safe-fraction arguments while keeping the base failure rate raw and every derating factor disclosed.
Apply the ISO 26262 transient rules
Pick a transient SPFM target or qualitative rationale and analyze transients separately from permanent faults.
Run a full transient FMEDA
Carry each element from raw FIT to residual rate, transient SPFM and a PMHF contribution you can defend to an assessor.
Chapter by chapter
- 01
When a Bit Flips
What a soft error actually is: a particle deposits charge, a storage node flips state, but the transistor is left perfectly healthy, unlike a permanent fault.
- Transient vs permanent: corrupted state, intact hardware
- Why a power cycle clears it and a stuck bit does not
- Critical charge and the node that lost its logic value
- 02
Where the Particles Come From
The three terrestrial radiation sources and why you cannot shield your way out of two of them.
- Atmospheric neutrons from cosmic-ray cascades, unshieldable
- Alpha particles from uranium, thorium and lead-210 in the package
- Thermal neutrons captured by boron-10 at ~3800 barns
- 03
The Single Event Zoo
The full taxonomy of single event effects, from soft upsets to destructive latch-up, mapped onto how ISO 26262 books each one.
- Soft side: SET, SEU, SBU, MCU, MBU, SEFI
- Destructive side: SEL, SEB, SEGR, SHE
- Why only the soft branch counts as a transient fault
- 04
Silicon Sensitivity & Measuring SER
How shrinking geometries and lower voltages change soft error behaviour, and how JESD89 accelerated beam testing turns cross-sections into FIT rates.
- Critical charge falling while multi-bit upsets rise with scaling
- Accelerated neutron and alpha testing per JESD89
- From measured cross-section to a raw FIT/Mbit number
- 05
From Raw SER to Effective Failure Rate
The masking and derating chain that separates raw upsets from failures that actually reach a safety goal, kept honest for the FMEDA.
- Logical, electrical and latching-window masking
- Architectural vulnerability factor and the safe fault fraction
- Why the base rate must stay raw, with derating disclosed
- 06
Detecting & Correcting: Codes and Scrubbing
The error-code ladder from parity to symbol codes, plus interleaving, scrubbing and the gaps ECC silently leaves open.
- SEC-DED at +8 bits per 64 as the safety-relevant default
- Bit interleaving that turns MBUs into correctable SBUs
- Scrubbing, address folding and CRC on configuration space
- 07
Hardening the Design
The six-layer defence-in-depth stack, from low-alpha packaging and DICE cells up to lockstep, TMR and system-level E2E.
- Hardened DICE cells for 1-2 orders of magnitude lower upset rate
- Lockstep CPU pairs and triple modular redundancy for the datapath
- Software and system layers that encode application knowledge
- 08
What ISO 26262 Says About Transients
The normative anchor points in Part 5 and Part 11, and the eight distilled rules for treating transient faults correctly.
- Dedicated transient SPFM target or a justified qualitative rationale
- Transients analyzed separately from permanent faults
- Radiation soft errors quantified; EMI transients stay systematic
- 09
Worked Example: A Transient FMEDA
A complete, reproducible transient FMEDA for a lockstep ASIL D microcontroller, every multiplication visible from raw rate to PMHF contribution.
- Three-factor pipeline: raw x non-safe fraction x escape probability
- 16 Mbit SRAM at 300 FIT/Mbit tamed by SEC-DED and scrubbing
- Transient SPFM split across RAM, logic and configuration
- 10
System View, Pitfalls & Checklist
How transients propagate beyond the chip, plus the most dangerous FMEDA mistakes and the assessor questions you must be ready for.
- Emerging trends: advanced nodes, safety islands, central compute
- Forgetting configuration registers and error accumulation
- Assessor checklist for safe-fraction and coverage claims
Not just text: the visual toolkit
Bit-Flip Charge Deposition
Traces a single particle from strike to deposited charge to a flipped storage node while the transistor stays intact.
Single Event Effect Family Tree
Splits every single event effect into the soft transient branch and the destructive permanent branch as ISO 26262 books them.
Masking & Derating Cascade
Shows how logical, electrical and latching-window masking plus the safe fraction reduce raw upsets to residual failures.
ECC, Interleaving & Scrubbing Map
Illustrates how bit interleaving and periodic scrubbing convert clustered multi-bit upsets into correctable single-bit errors.
Defence-in-Depth Hardening Stack
Layers process and package, hardened cells, ECC, lockstep, software and system measures into one protection story.
Transient FMEDA Pipeline
Walks each element from raw FIT through non-safe fraction and coverage to a transient SPFM and PMHF contribution.
Transient FMEDA for a Lockstep ASIL D Microcontroller
A fictional but realistic lockstep MCU subsystem implements an ASIL D torque-limitation function, sized so you can follow every multiplication. Each element is carried through the three-factor pipeline, from a 16 Mbit SRAM at 300 FIT/Mbit down to a residual transient failure rate, then rolled up into a transient SPFM and a PMHF contribution.
- System SRAM: 4800 raw FIT, 50% safe fraction, SEC-DED plus 4-way interleaving and 1 h scrubbing at 99.9% DC
- CPU lockstep flip-flops: 200 raw FIT, 60% safe by AVF fault injection, delayed lockstep with a layout-diverse shadow core at 99% DC
- Configuration registers: 15 raw FIT, only 20% safe, register parity plus a 100 ms golden-image CRC at 90% DC
- Flash controller buffers: 20 raw FIT, protected end-to-end by buffer and line ECC into the bus at 99% DC
- Bus fabric, DMA and misc logic: 100 raw FIT, bus parity and DMA descriptor CRC with E2E on safety payloads at 95% DC
- Residuals rolled up into a transient SPFM, split across RAM and logic, then folded into the PMHF budget
Unlock the full 5-element FMEDA table with residuals, transient SPFM split and the PMHF contribution
Who this guide is for
- Hardware safety engineers who must add a transient column to their FMEDA
- SoC and memory designers choosing between ECC schemes, interleaving, and scrubbing
- FMEDA reviewers asked to judge a supplier's soft error rate derating
- Engineers hearing "cosmic rays" in a design review and wanting the real physics
Frequently Asked Questions
Common questions about Soft Errors & Transient Faults
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