Soft Errors & Transient Faults
10 chapters A single cosmic-ray neutron or a package alpha particle can flip a bit in your ASIL D microcontroller and leave the silicon undamaged. This concept takes you from the physics of radiation-induced bit flips through the full single event effect zoo, ECC and hardened design, to a reproducible ISO 26262 Part 11 transient FMEDA.
How You Learn
Video and text stay in sync. As you scroll through the chapter, the video jumps to the matching explanation automatically.
Learning Objectives
Tell transient from permanent faults
Explain why a soft error clears on power cycle while a stuck bit does not, and book each on the right FMEDA side.
Name and place every single event effect
Distinguish SET, SEU, MCU, MBU and SEFI from destructive SEL, SEB, SEGR and SHE and classify them per Part 11.
Size ECC, interleaving and scrubbing
Choose SEC-DED versus stronger codes and set interleaving and scrub intervals to hit a transient coverage target.
Derate raw SER without cheating
Apply masking and safe-fraction arguments while keeping the base failure rate raw and every derating factor disclosed.
Chapters
When a Bit Flips
What a soft error actually is: a particle deposits charge, a storage node flips state, but the transistor is left perfectly healthy, unlike a permanent fault.
Where the Particles Come From
The three terrestrial radiation sources and why you cannot shield your way out of two of them.
The Single Event Zoo
The full taxonomy of single event effects, from soft upsets to destructive latch-up, mapped onto how ISO 26262 books each one.
Silicon Sensitivity & Measuring SER
How shrinking geometries and lower voltages change soft error behaviour, and how JESD89 accelerated beam testing turns cross-sections into FIT rates.
From Raw SER to Effective Failure Rate
The masking and derating chain that separates raw upsets from failures that actually reach a safety goal, kept honest for the FMEDA.
Detecting & Correcting: Codes and Scrubbing
The error-code ladder from parity to symbol codes, plus interleaving, scrubbing and the gaps ECC silently leaves open.
Hardening the Design
The six-layer defence-in-depth stack, from low-alpha packaging and DICE cells up to lockstep, TMR and system-level E2E.
What ISO 26262 Says About Transients
The normative anchor points in Part 5 and Part 11, and the eight distilled rules for treating transient faults correctly.
Worked Example: A Transient FMEDA
A complete, reproducible transient FMEDA for a lockstep ASIL D microcontroller, every multiplication visible from raw rate to PMHF contribution.
System View, Pitfalls & Checklist
How transients propagate beyond the chip, plus the most dangerous FMEDA mistakes and the assessor questions you must be ready for.
Diagrams & Visuals
Bit-Flip Charge Deposition
Traces a single particle from strike to deposited charge to a flipped storage node while the transistor stays intact.
Single Event Effect Family Tree
Splits every single event effect into the soft transient branch and the destructive permanent branch as ISO 26262 books them.
Masking & Derating Cascade
Shows how logical, electrical and latching-window masking plus the safe fraction reduce raw upsets to residual failures.
ECC, Interleaving & Scrubbing Map
Illustrates how bit interleaving and periodic scrubbing convert clustered multi-bit upsets into correctable single-bit errors.
Defence-in-Depth Hardening Stack
Layers process and package, hardened cells, ECC, lockstep, software and system measures into one protection story.
Transient FMEDA Pipeline
FeaturedWalks each element from raw FIT through non-safe fraction and coverage to a transient SPFM and PMHF contribution.
Explore SimulatorsTransient FMEDA for a Lockstep ASIL D Microcontroller
A fictional but realistic lockstep MCU subsystem implements an ASIL D torque-limitation function, sized so you can follow every multiplication. Each element is carried through the three-factor pipeline, from a 16 Mbit SRAM at 300 FIT/Mbit down to a residual transient failure rate, then rolled up into a transient SPFM and a PMHF contribution.
- System SRAM: 4800 raw FIT, 50% safe fraction, SEC-DED plus 4-way interleaving and 1 h scrubbing at 99.9% DC
- CPU lockstep flip-flops: 200 raw FIT, 60% safe by AVF fault injection, delayed lockstep with a layout-diverse shadow core at 99% DC
- Configuration registers: 15 raw FIT, only 20% safe, register parity plus a 100 ms golden-image CRC at 90% DC
- Flash controller buffers: 20 raw FIT, protected end-to-end by buffer and line ECC into the bus at 99% DC
- Bus fabric, DMA and misc logic: 100 raw FIT, bus parity and DMA descriptor CRC with E2E on safety payloads at 95% DC
- Residuals rolled up into a transient SPFM, split across RAM and logic, then folded into the PMHF budget
Transient FMEDA Roll-Up (fictional lockstep MCU)
Master Soft Errors From Physics to a Defensible FMEDA
Work through the single event zoo, ECC and hardening choices, the ISO 26262 Part 11 rules and a fully worked transient FMEDA for a lockstep ASIL D microcontroller.
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