Title: ISO 26262 and Semiconductors | ISO 26262 Academy URL: https://iso26262.academy/features/concepts/iso-26262-semiconductors Description: Practical handbook for applying ISO 26262 Part 11 to digital, analog, programmable logic, multi-core SoCs, and sensor silicon. --- Concept guide · ISO 26262-11 · 12 chapters # ISO 26262 and Semiconductors A practical handbook for applying ISO 26262 Part 11 across digital, analog, programmable logic, multi-core SoC and sensor silicon. The standard, the annexes and the assessor-ready evidence trail, with worked FMEDA, DC, DFA and fault-injection examples. 12 Chapters 60+ Diagrams & Tables Annex C/D/E Worked Examples Part 11 Clause-by-Clause Included in Expert [Start learning](https://iso26262.academy/register?plan=free&from=%2Fconcepts%2Fiso-26262-semiconductors&utm_source=website&utm_medium=cta&utm_campaign=features_concepts) See the chapters Inside the course 1. 01 **Why Silicon Is Different** 2. 02 **Part 11 Map: Clauses & Annexes** 3. 03 **Failure Physics in Silicon** 4. 04 **Hardware Element Catalog** 5. 05 **Distributed Development & IC as SEooC** The short version ## Quick answers What is ISO 26262 Part 11? ISO 26262-11, added in the 2018 edition, is the guideline part on applying ISO 26262 to semiconductors. It exists because silicon breaks the assumptions of Parts 1 to 10: failure rates are not constant across the bathtub curve, transient soft errors dominate at advanced nodes, and an IC is almost always developed as a Safety Element out of Context, before any specific vehicle item exists. Part 11 covers digital, analog, programmable logic, multi-core SoC and sensor elements, with informative annexes providing worked examples - including the Annex C die-plus-package FMEDA, Annex D analog examples and Annex E programmable logic examples this guide walks end to end. How do you calculate FIT rates for a chip? The Part 11 approach decomposes the IC into die and package contributions. Base rates come from handbooks such as SN 29500, IEC 61709 or FIDES, corrected for the mission profile, and the die rate is then allocated across functional blocks - CPU, SRAM, peripherals - with refinements beyond pure area proportionality. The Annex C worked example computes roughly 0.26 FIT for the die and 12.41 FIT for the package of a CMOS digital MCU, around 13 FIT total, with soft-error rates from the JEDEC JESD89 framework added separately because transient upsets scale differently with technology node than permanent faults do. Keep going, free - [Demo exam · no account Test yourself with 7 exam-style questions](https://iso26262.academy/demo-exam) Why this course · ISO 26262, Part 11 ## Why it pays for itself ### Apply Part 11 by IC family Identify whether your element is digital, analog, programmable logic, multi-core SoC or sensor silicon, and select the matching Part 11 clause and supporting annex with a defensible justification. ### Build a silicon-level FMEDA Decompose die plus package FIT following the Annex C worked example, classify safe faults from the exposure window, and refine block-level allocation beyond naive area proportionality. ### Quantify and prove diagnostic coverage Split DC between permanent and transient faults across ECC, lockstep, BIST, window comparators and scrubbing, then back the numbers with a properly planned fault-injection campaign. After the course ## What you’ll be able to do ### Apply Part 11 by IC Family Identify whether your element is digital, analog, PLD, multi-core SoC or sensor and select the correct Clause 5.x and supporting annex with justification. ### Build a Defensible FMEDA at Silicon Level Decompose die plus package FIT, classify safe faults from the exposure window, and refine block-level allocation beyond pure area proportionality. ### Quantify DC for Real Safety Mechanisms Split DC for permanent and transient faults across memory ECC, lockstep, BIST, window comparators and scrubbing, and back the number with fault-injection evidence. ### Run DFA on Shared Silicon Resources Identify Annex B coupling paths (clock, power, reset, substrate, thermal) and verify that any independence claim is supported by a documented DFA report. ### Plan a Fault-Injection Campaign Specify all six mandatory planning fields, choose the right abstraction (RTL, gate, emulation, beam), and qualify the EDA fault simulator per Part 8 §11. ### Ship an Assessor-Ready Safety Case Assemble the eight Part 11 work products, populate the ten safety-manual sections, and close every Assumption of Use through the DIA before the assessment. The curriculum · 12 chapters ## Chapter by chapter 1. 01 **Why Silicon Is Different** Why constant-FIT models and Parts 1-10 assumptions break at advanced nodes. - Bathtub vs constant FIT - Scale, physics, distribution - IC as SEooC by default 2. 02 **Part 11 Map: Clauses & Annexes** Navigate Clause 4, the five technology-specific clauses, and the six informative annexes. - Clause 4 + 5.x structure - Annexes A-F templates - Hooks to Parts 4-10 3. 03 **Failure Physics in Silicon** Permanent, transient, destructive and wear-out faults with JESD89C soft-error framework. - Four failure classes - JESD89C soft-error framework - Node-scaling SER formula 4. 04 **Hardware Element Catalog** Digital, analog, PLD, multi-core SoC and sensor families with per-family fault landscapes. - Five element families - Per-family fault landscape - Allocation methods 5. 05 **Distributed Development & IC as SEooC** IP vendor, foundry, OSAT and integrator collaborating through testable Assumptions of Use. - SEooC framework - AoU: testable, owned, dated - Safety manual contract 6. 06 **Quantifying FIT in Silicon** Handbook selection, die plus package decomposition and safe-fault exposure-window classification. - SN 29500, IEC 61709, FIDES - Annex C worked example - Safe-fault exposure window 7. 07 **On-Chip Safety Mechanisms & DC** Diagnostic Coverage split for permanent and transient faults across memory, digital and analog SMs. - DC buckets: Low/Med/High - ECC, lockstep, BIST - Permanent vs transient split 8. 08 **DFA at Silicon Level** Shared clock, power, reset and substrate make CCF the default; Annex B starter-list DFIs. - Five coupling mechanisms - Annex B starter DFIs - Replica PLL & supply isolation 9. 09 **Multi-core & SoC Patterns** Homogeneous lockstep, heterogeneous safety island, and asymmetric monitoring patterns. - Lockstep variants - Safety island - Shared-resource exposure 10. 10 **Fault Injection & EDA Qualification** Six mandatory campaign fields and EDA tool qualification per Part 8 §11. - Six planning fields - RTL/gate/emulation/beam - EDA TCL per Part 8 §11 11. 11 **Analog, PLD and Sensors** Annex D analog window comparators, Annex E PLD bitstream scrubbing, sensor plausibility checks. - Annex D analog example - Annex E PLD scrubbing - Sensor self-test 12. 12 **Work Products & Pitfalls** Eight work products, ten safety-manual sections, and twelve recurring audit findings. - 8 work products - 10 manual sections - 12 audit pitfalls Interactive Diagrams & Worked Examples ## Not just text: the visual toolkit ### Part 11 Clause Map Navigate Clause 4 (general) and Clauses 5.1-5.5 (digital, analog, PLD, multi-core, sensors) plus the six informative annexes with cross-references to Parts 4-10. ### Die + Package FMEDA Worked Example Annex C numerical breakdown of a CMOS digital MCU: 0.26 FIT die (CPU, SRAM, peripherals) plus 12.41 FIT package, summed to ~13 FIT total IC with soft-error from JESD89 added separately. ### On-Chip Safety Mechanism Cards Per-mechanism cards for parity, SECDED, MBU strategies, scrubbing, LBIST, lockstep, window comparator and ABIST, each showing permanent and transient DC bars and the failures missed. ### Multi-core Lockstep Pattern Comparison Pure, delayed and asymmetric lockstep variants with mini block diagrams, DC formulas under the independence assumption, and the shared-resource DFIs that defeat it. ### Fault-Injection Campaign Planner Six mandatory planning fields (fault model, abstraction, fault list, workload, observation points, method) with worked example: 42k faults, post-synthesis gates, AEB workload, DC = 94.2%. ### Analog Window Comparator & PLD Scrubbing Annex D LDO with window comparator (99% perm DC, 60% aging via ABIST) plus Annex E SRAM-FPGA bitstream residual SEU after 100 ms scrubbing over an 8000 h mission. Annex-Aligned Worked Examples ## Annex C, D and E Worked Through End to End Each chapter is anchored in a Part 11 annex example so the math stays reproducible. - Annex C digital FMEDA: die + package decomposition - Annex D analog: window comparator and ABIST - Annex E PLD: SRAM-FPGA bitstream scrubbing - Fault-injection campaign with DC and confidence interval - Safety manual AoU template ready for the DIA Annex C Die + Package FMEDA Die + package FIT decomposition for a CMOS digital MCU Unlock the full worked examples Built for ## Who this guide is for - IC and IP safety engineers producing Part 11 work products and safety manuals - SoC architects choosing between lockstep, safety island and asymmetric monitoring patterns - Tier 1 and OEM integrators who must read supplier safety manuals and close Assumptions of Use - Field application engineers supporting automotive customers with functional safety questions ## Frequently Asked Questions Common questions about ISO 26262 and Semiconductors A chip is designed years before it lands in any specific vehicle item, so the IC vendor cannot know the actual safety goals - they develop it as a Safety Element out of Context (SEooC) against assumed requirements. Those assumptions are captured as Assumptions of Use (AoU) in the safety manual: testable, owned, dated statements about how the integrator must configure and use the device for the safety claims to hold. The integrator must verify every AoU in the real item context - typically through the Development Interface Agreement - and an unclosed AoU is one of the most common findings in a semiconductor safety assessment. The workhorse mechanisms are memory protection (parity, SECDED ECC, scrubbing against accumulating soft errors), core-level redundancy (pure, delayed or asymmetric lockstep), structural self-test (LBIST for logic, ABIST for analog), and analog supervision such as window comparators on supplies. Each mechanism has a different diagnostic coverage profile for permanent versus transient faults - lockstep catches both, ECC handles transient bit flips, LBIST finds permanent faults only at test time - and shared clock, power, reset and substrate make dependent failures the default assumption, so a DFA against the Annex A coupling mechanisms accompanies any independence claim. The guide has 12 chapters spanning failure physics in silicon, the Part 11 clause map, the five hardware element families, SEooC development, FIT quantification, on-chip safety mechanisms, dependent failure analysis, multi-core patterns, fault injection and EDA tool qualification, and the Part 11 work products - supported by more than 60 diagrams and tables. The Annex C, D and E worked examples are carried through end to end so the numbers stay reproducible. A free account starts you off, and the Pro and Expert plans unlock more of the library. ## Start the course today A free account unlocks one full concept guide, 3 work product templates, 1 guided process, the Markov simulator, and 5 practice exams per month. The Pro and Expert plans unlock more of the 78-guide library. No credit card required. [Start learning](https://iso26262.academy/register?plan=free&from=%2Fconcepts%2Fiso-26262-semiconductors&utm_source=website&utm_medium=cta&utm_campaign=features_concepts) [View Pricing Plans](https://iso26262.academy/pricing)